A regulated cross-couple charge pump with new charging current smoothing technique is proposed and verified in a 0.18-μm 1.8-V/3.3-V CMOS process. The transient behaviors of 3-stage cross-couple charge pump and the expressions for the charging current are described in detail. The experiment results show that the charging current ripples are reduced by a factor of […]
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研究成果
A CMOS-Process-Compatible Low-Voltage Junction-FET With Adjustable Pinch-Off Voltage
A novel horizontal n-channel junction field effect transistor (n-JFET) device is proposed and verified in a 0.25-µm bulk CMOS process. This horizontal JFET consists of alternating n- and p-regions formed by using the P-type electro-static discharge (ESD) implantation. P-type ESD implantation has been an optional and commonly well supported process step by most of foundries […]
Investigation on Unexpected Latchup Path between HV-LDMOS and LV-CMOS in a 0.25-μm 60-V/5-V BCD Technology
The latchup path which may potentially exist at the interface between high-voltage (HV) and low-voltage (LV) circuits in a HV bipolar-CMOS-DMOS (BCD) technology is investigated in this work. Owing to the multiple well structures used to realize the HV device in the BCD process, the expected latchup path in the test structure was hardly triggered. […]